Quantum Tunneling enables Ultra-Low Area and Power Neural Network for Brain Scale Computing
Image credit: Ankit Bende
Brain-scale Computing is a Decadal Challenge
The biology of the brain enables approximate computing with analog synapses that connect stochastic and digital spiking neurons. Along with fascinating connectivity schemes, this results in the power & mystique of the biological brain that chaperones all the processes of human thought and action.
As humans build next-generation AI-powered sensors & computing, the biological brain remains an inspiration and an enigma! A measure of understanding the brain enigma is our ability to build a brain-like computing platform. A successful brain-scale emulator could enable revolutionary advancements from sentient autonomous, self-learning bots to understanding diseases of the brain.
Mainstream computing technology using transistors to make digital gates has taken over the world. This technology enables Boolean logic with Very Large-Scale Integration (VLSI) of transistors to form complex circuits including microprocessors. Yet, mimicking a complex mix of analog, stochastic, and digital processing in the biological brain at scale using traditional digital computing technology has significant inefficiencies. This makes brain-scale computing, i.e. replicating the brain with its 100 billion neurons with 1 quadrillion (i.e. 1000 trillion) synapses, a daunting task.
Adapting Silicon Technology to Mimic the Brain
A promising approach is to adapt the mature silicon technology by leveraging hitherto untapped physics to design & build efficient neurons and synapses to create neuro-synaptic cores. These cores are akin to microprocessor cores, except for working on biological principles of computing. To ensure an efficient core, the neuronal design must be very energy and area efficient. This requires a compact and ultra-low current source in silicon technology – a central challenge.
In 2021, the researchers from IIT Bombay led by Prof. Udayan Ganguly proposed the use of quantum tunneling current in a silicon on insulator (SOI) technology as a solution. The quantum tunneling current levels are close to the off-current level of a traditional transistor. The off-current is 10000 times smaller than the typical on-currents used in transistors. This enables significant power and area savings!
To take the innovation to the next systems level, a device-circuit-algorithm co-design team was formed led by Prof. Udayan Ganguly and Prof. Maryam Shojaei Baghini at IIT Bombay. Together, the team has designed the global first spiking neuro-synaptic core on 45nm SOI technology. The team coordinated remotely from their respective homes during Covid 19 lockdown, thanks to the online computing infrastructure at IIT Bombay.
Algorithm-Circuit-Device Co-design by IIT Bombay Team
The application was speech recognition using a neural network algorithm inspired by the auditory cortex. A spoken word recognition algorithm, the Liquid State Machine, uses the idea that the neural network forms a neuronal reservoir which is analogous to a liquid reservoir. Spoken words are like liquid droplets falling on the reservoir surface creating ripples. The ripples capture the memory of the spoken word in time to enable a simple classifier layer to classify accurately.
A graduate student Vivek Saraswat worked on adapting this algorithm to hardware by adding the various hardware quirks to the conventional “ideal” software implementations to show the feasibility of the hardware implementation. The quirks include variability and non-linearities of “physical” elements like neurons and synapses implemented on silicon technology.
Another graduate student, Ajay Singh, led the circuit demonstration. He implemented a 20-neuron input layer that fed the neural spike signal into a 36-neuron reservoir where neurons were connected in a random recurrent manner through 256 synapses. Some of the critical hardware “quirks” identified in algorithms were mitigated through design. A key challenge was that tunneling is by nature exponentially dependent on the input voltage to produce a non-linear current source. However, software algorithms assume a linear current source. Ajay designed correction blocks to enable “ideal” neurons. Such control ensures that the large body of algorithms can be implemented in our hardware directly without redesign.
Achieving performance using 45nm Silicon Technology at GlobalFoundries
The neural network circuit was designed & fabricated on the mature 45RFSOI technology. The chip manufacturing was supported through the prestigious GlobalFoundries University Program. Dr. Ted Letavic, CTO of Compute and Wired Infrastructure Business Unit at GF commented that “This is pioneering work that showcases the advantages of mature SOI technology to demonstrate a new neural compute paradigm based on quantum tunneling."
As the world’s first neuro-synaptic core leveraging advanced SOI technology, the study has been recently accepted for publication in IEEE Transactions of Circuits and Systems in 2022. The IEEE publication highlights that the team has achieved 5000 times lower energy-per-spike at a similar area, 50 times less area at a similar energy-per-spike, and 10 times lower standby power at a similar area and energy-per-spike compared to the state-of-the-art benchmarks. Such overall performance improvement enables brain-scale computing.
AI chips from India’s innovation ecosystem for global leadership
As semiconductor ecosystem development becomes a national priority with the cabinet approval of the 10 Billion USD investment in India and AI Hardware development acquires global focus, Prof. Ajay Sood, Principal Scientific Advisor (PSA) to the Government of India remarked “Demonstrating silicon-proven ideas based on an untapped quantum phenomenon in silicon to build efficient brain-like computing is promising on the global scale. The confluence of the national semiconductors priority as well as the emergence of AI and brain-scale computing hardware as the R&D focus at the global level makes the demonstration very timely and compelling.”
The work was initiated under DST Nanomission and later supported by Nanoelectronics Network for Research & Applications (NNetRA) funded by MeitY & DST. On an IIT Bombay team achieving this milestone, Dr. V.K. Saraswat, Member, NITI Aayog commented that “India has excellent strength in circuit design. Advanced technology-circuits-systems co-design is the “holy grail”. A new computing hardware platform demonstrated by the IIT Bombay team based on advanced devices-circuit-system co-design is an exemplary demonstration. It contains the essence of the deep knowledge of technology, device, and circuits developed in the Centers of Excellence in Nanoelectronics (CENs) leading to such pathbreaking inventions. As a next step, brain-scale computing enabled my nanoelectronics should become a major thrust in India’s S&T program to amplify the scope and ambition of such research towards new products and capabilities.”
Source: IIT Bombay news release: Author: Ankit Bende